Low-k dielectric materials are dielectric materials having a dielectric constant (k) lower than that of thermal silicon dioxide (i.e., k<3.9). The minimum value of k is 1.0 for air. Hence, Low-k dielectric materials are dielectric material having a dielectric constant between 1.0 and 3.9.
The use of low-k dielectric materials are important in the advancement of integrated circuit applications for semiconductor devices. One advantageous use of low-k materials in semiconductor devices is between conductor lines or structures (e.g., intermetal dielectric structures). The RC delay in switching is one factor that limits the operating speed of semiconductor devices. Generally as RC delay increases, the maximum operating speed of a semiconductor device decreases. RC delay can be reduced by decreasing resistance (R) in the conducting lines/structures and/or by decreasing the parasitic capacitance (C) developed between conducting lines/structures. This parasitic capacitance can be reduced by using dielectric materials with smaller permittivity values, which low-k dielectric materials provide.
One of the primary dielectric materials of choice for use between conducting lines in an intermetal dielectric structure has been silicon dioxide (SiO2) due to its dielectric characteristics, its mechanical strength, and its ease of processing. However, silicon dioxide typically has a dielectric constant ranging from k=3.9 to 4.5, depending on the method of forming it. This k value is too high for most integrated circuit applications below about 0.18 μm. Thus, as the geometries of semiconductor devices have continued to shrink, there has been a push to develop and use new dielectric materials with dielectric-constant values much lower than that of silicon dioxide, i.e., low-k dielectric materials.
There are many trade-offs that must be considered when attempting to implement a low-k dielectric material. For example, the mechanical strength and mechanical performance of low-k materials typically decreases as the value of k decreases. Also, many low-k dielectric materials having desirable electrical properties may be incompatible with other adjacent materials and/or processes used to form or process such adjacent materials. Thus, a need exists for ways to implement low-k dielectric materials to obtain the lowered parasitic capacitance advantages even though such low-k dielectric materials may have less mechanical strength and/or incompatibility issues.
FIG. 1 shows a conventional intermetal dielectric structure 20 formed using single damascene and dual damascene processes, for example. In forming the structure 20 of FIG. 1 using conventional processes, a dielectric layer 21 is typically formed first. Then, a hard mask layer 24 is formed and patterned. Next, openings for conductor lines 26 and vias 28 are patterned, etched, and filled with a liner layer 30 and a conductive material (e.g., aluminum, copper, and/or tungsten). Thus, the dielectric layer 21 is present during several subsequent processing steps, any of which could have the potential to damage, change, or negatively affect the dielectric layer 21 (i.e., being incompatible with the dielectric layer 21).
Usually in a conventional damascene process of forming an intermetal dielectric structure 20 (e.g., as shown in FIG. 1), several integration issues must be addressed with respect to the choice of low-k dielectric material utilized for the dielectric layer 21. The low-k dielectric material usually needs to be mechanically strong and structurally stable. The low-k dielectric material typically needs to be CMP compatible (chemically and mechanically) to withstand any CMP processes involved while the dielectric material is present. Because a hard mask 24 is frequently used during the damascene processing, the low-k dielectric material may need to be compatible with the hard mask material and processes for forming, patterning, and/or removing the hard mask layer 24. Furthermore, the low-k dielectric material chosen will usually need to be compatible with the liner deposition and/or conductor deposition processes.
Because there are so many compatibility issues to consider when trying to implement, introduce, or test a new low-k dielectric material into a conventional intermetal dielectric structure 20 (see e.g., FIG. 1), the complexity, time, and cost of developing and testing new low-k dielectrics can be quite large. Hence, there is a need for a way to reduce the complexity, time, and cost of testing and implementing new low-k materials.